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? semiconductor components industries, llc, 2011 october, 2011 ? rev. 1 1 publication order number: ncp1234/d ncp1234 fixed frequency current mode controller for flyback converters the ncp1234 is a new fixed ? frequency current ? mode controller featuring dynamic self ? supply (dss). this device is pin ? to ? pin compatible with the previous ncp12xx families. the dss function greatly simplifies the design of the auxiliary supply and the v cc capacitor by activating the internal startup current source to supply the controller during transients. due to frequency foldback, the controller exhibits excellent efficiency in light load condition while still achieving very low standby power consumption. internal frequency jittering, ramp compensation, and a versatile latch input make this controller an excellent candidate for converters where components cost is the key constraints. it features a timer ? based fault detection that ensures the detection of overload independently of an auxiliary winding, and an adjustable compensation to help keep the maximum power independent of the input voltage. finally, due to a careful design, the precision of critical parameters is well controlled over the entire temperature range ( ? 40 ? c to +125 ? c). features ? fixed ? frequency current ? mode operation with built ? in ramp compensation ? 65 khz or 100 khz oscillator frequency version ? frequency foldback then skip mode for maximized performance in light load and standby conditions ? timer ? based overload protection with latched (option a) or auto ? recovery (option b) operation ? high ? voltage current source with dynamic self ? supply, simplifying the design of the v cc capacitor ? frequency modulation for softened emi signature, including during frequency foldback mode ? adjustable overpower compensation ? latch ? off input for severe fault conditions, allowing direct connection of an ntc for overtemperature protection (otp) ? v cc operation up to 28 v, with overvoltage detection ? ? 500 ma peak source/sink current drive capability ? 4.0 ms soft ? start ? internal thermal shutdown ? pin ? to ? pin compatible with the existing ncp12xx series ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? ac ? dc adapters for notebooks, lcd, and printers ? offline battery chargers ? consumer electronic power supplies ? auxiliary/housekeeping power supplies soic ? 7 case 751u marking diagram http://onsemi.com 34xff alywx 1 8 34xff = specific device code x = a or b ff = 65 or 100 a = assembly location l = wafer lot y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 32 of this data sheet. ordering information 18 5 3 4 (top view) latch cs hv pin connections 6 2 fb gnd drv v cc
ncp1234 http://onsemi.com 2 typical application example vout vin (dc) ncp1234 latch fb cs gnd hv vcc drv figure 1. flyback converter application using the ncp1234 pin function description pin no pin name function pin description 1 latch latch ? off input pull the pin up or down to latch ? off the controller. an internal current source allows the direct connection of an ntc for over temperature detection 2 fb feedback an optocoupler collector to ground controls the output regulation. 3 cs current sense this input senses the primary current for current ? mode operation, and offers an overpower compensation adjustment. 4 gnd ic ground 5 drv drive output drives external mosfet 6 v cc v cc input this supply pin accepts up to 28 vdc, with overvoltage detection 8 hv high ? voltage pin connects to the bulk capacitor or the rectified ac line to perform the functions of start ? up current source and dynamic self ? supply
ncp1234 http://onsemi.com 3 simplified internal block schematic figure 2. simplified internal block schematic cs fb ? + t leb blanking / 5 t fault timer v fb(ref) 20 k ? + ? + + ? + + v ilim v cs(stop) s r q t sstart soft ? start ramp start reset ic start ic stop oscillator hv v cc latch ? + + v skip protection mode release drv hv clamp fault sawtooth jitter v to i hv sample i opc = 0.5 x (v hv ? 125) ? + + v fb(opc) latch dual hv start ? up current source v cc management hv current tsd v dd uvlo reset tsd start ic start pwm soft ? start i limit vdd uvlo ic stop tsd tsd i limit pwm fault flag foldback gnd stop s r q t bcs blanking ? + v ovp s r q ? + v otp t latch(ovp) blanking v dd reset latch v clamp i ntc t latch(otp) blanking 1 k i ntc + + soft ? start end soft ? start end end slope comp. uvlo reset t autorec timer for autorecovery protection mode only
ncp1234 http://onsemi.com 4 maximum ratings rating symbol value unit supply pin (pin 6) (note 2) voltage range current range v ccmax i ccmax ?0.3 to 28 ? 30 v ma high voltage pin (pin 8) (note 2) voltage range current range v hvmax i hvmax ?0.3 to 500 ? 20 v ma driver pin (pin 5) (note 2) voltage range current range v drvmax i drvmax ?0.3 to 20 ? 1000 v ma all other pins (note 2) voltage range current range v max i max ?0.3 to 10 ? 10 v ma thermal resistance soic ? 7 junction ? to ? air, low conductivity pcb (note 3) junction ? to ? air, medium conductivity pcb (note 4) junction ? to ? air, high conductivity pcb (note 5) r ? j ? a 162 147 115 ? c/w temperature range operating junction temperature storage temperature range t jmax t strgmax ? 40 to +150 ? 60 to +150 ? c esd capability (note 1) human body model (all pins except hv) machine model 2000 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22, method a114e machine model method 200 v per jedec standard jesd22, method a115a 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78 3. as mounted on a 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 ? 1 conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 80 x 100 x 1.5 mm fr4 substrate with a single layer of 100 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 ? 2 conductivity test pcb. test conditions were under natural convection or zero air flow. 5. as mounted on a 80 x 100 x 1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 ? 3 conductivity test pcb. test conditions were under natural convection or zero air flow.
ncp1234 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 ? c, for min/max values t j = ? 40 ? c to +125 ? c, v hv = 125 v, v cc = 11 v unless otherwise noted) characteristics test condition symbol min typ max unit high voltage current source minimum voltage for current source operation v hv(min) ? 30 60 v current flowing out of v cc pin v cc = 0 v v cc = v cc(on) ? 0.5 v i start1 i start2 0.2 3 0.5 6 0.8 9 ma off ? state leakage current v hv = 500 v i start(off) ? 25 50 a supply turn ? on threshold level, v cc going up hv current source stop threshold v cc(on) 11.0 12.0 13.0 v hv current source restart threshold v cc(min) 9.5 10.5 11.5 v turn ? off threshold v cc(off) 8.5 9.5 10.5 v overvoltage threshold v cc(ovp) 25 26.5 28 v blanking duration on v cc(off) and v cc(ovp) detection t vcc(blank) 7 10 13 s v cc decreasing level at which the internal logic resets v cc(reset) 3.6 5.0 6.0 v v cc level for i start1 to i start2 transition v cc(inhibit) 0.4 1.0 1.6 v internal current consumption (note 6) drv open, v fb = 3 v, 65 khz drv open, v fb = 3 v, 100 khz c drv = 1 nf, v fb = 3 v, 65 khz c drv = 1 nf, v fb = 3 v, 100 khz off mode (skip or before start ? up) fault mode (fault or latch) i cc1 i cc1 i cc2 i cc2 i cc3 i cc4 1.2 1.3 1.9 2.2 0.67 0.4 1.8 1.9 2.5 2.9 0.9 0.7 2.2 2.3 3.2 3.6 1.13 1.0 ma oscillator oscillator frequency f osc 60 92 65 100 70 108 khz maximum duty cycle d max 75 80 85 % frequency jittering amplitude, in percentage of f osc a jitter ? 4 ? 6 ? 8 % frequency jittering modulation frequency f jitter 85 125 165 hz output driver rise time, 10% to 90 % of v cc v cc = v cc(min) + 0.2 v, c drv = 1 nf t rise ? 40 70 ns fall time, 90% to 10 % of v cc v cc = v cc(min) + 0.2 v, c drv = 1 nf t fall ? 40 70 ns current capability v cc = v cc(min) + 0.2 v, c drv = 1 nf drv high, v drv = 0 v drv low, v drv = v cc i drv(source) i drv(sink) ? ? 500 500 ? ? ma clamping voltage (maximum gate voltage) v cc = v ccmax ? 0.2 v, drv high, r drv = 33 k , c load = 220 pf v drv(clamp) 11 13.5 16 v high ? state voltage drop v cc = v cc(min) + 0.2 v, r drv = 33 k , drv high v drv(drop) ? ? 1 v 6. internal supply current only, current in fb pin not included (current flowing in gnd pin only).
ncp1234 http://onsemi.com 6 electrical characteristics (for typical values t j = 25 ? c, for min/max values t j = ? 40 ? c to +125 ? c, v hv = 125 v, v cc = 11 v unless otherwise noted) characteristics test condition symbol min typ max unit feedback internal pull ? up resistor t j = 25 ? c r fb(up) 15 20 25 k v fb to internal current setpoint division ratio k fb 4.7 5 5.3 ? internal pull ? up voltage on the fb pin v fb(ref) 4.3 5 5.7 v current sense input bias current v cs = 0.7 v i bias ? 0.02 ? a maximum internal current setpoint v fb > 3.5 v v ilim 0.66 0.7 0.74 v propagation delay from v ilimit detection to drv off v cs = v ilim t delay ? 80 110 ns leading edge blanking duration for v ilim t leb 190 250 310 ns threshold for immediate fault protection activation v cs(stop) 0.95 1.05 1.15 v leading edge blanking duration for v cs(stop) t bcs 90 120 150 ns slope of the compensation ramp s comp(65khz) s comp(100khz) ? ? ? 32.5 ? 50 ? ? mv / s soft ? start duration from 1 st pulse to v cs = v ilim t sstart 2.8 4.0 5.2 ms overpower compensation v hv to i opc conversion ratio k opc ? 0.54 ? a / v current flowing out of cs pin v hv = 125 v v hv = 162 v v hv = 325 v v hv = 365 v i opc(125) i opc(162) i opc(325) i opc(365) ? ? ? 105 0 20 110 130 ? ? ? 150 a fb voltage above which i opc is applied v hv = 365 v v fb(opcf) 2.12 2.35 2.58 v fb voltage below which is no i opc applied v hv = 365 v v fb(opce) ? 2.15 ? v watchdog timer for dc operation t wd(opc) ? 32 ? ms hv sampling level v hvsample ? 92 ? v overcurrent protection fault timer duration from cs reaching v ilimit to drv stop t fault 98 128 168 ms autorecovery mode latch ? off time duration t autorec 0.85 1.00 1.35 s frequency foldback feedback voltage threshold below which frequency foldback starts v fb(folds) 1.8 2.0 2.2 v feedback voltage threshold below which frequency foldback is complete v fb(folde) 1.22 1.35 1.48 v minimum switching frequency v fb = v skip(in) + 0.2 f osc(min) 22 27 32 khz skip ? cycle mode feedback voltage thresholds for skip mode v fb going down v fb going up v skip(in) v skip(out) 0.63 0.72 0.7 0.80 0.77 0.88 v
ncp1234 http://onsemi.com 7 electrical characteristics (for typical values t j = 25 ? c, for min/max values t j = ? 40 ? c to +125 ? c, v hv = 125 v, v cc = 11 v unless otherwise noted) characteristics unit max typ min symbol test condition latch ? off input high threshold v latch going up v ovp 2.35 2.5 2.65 v low threshold v latch going down v otp 0.76 0.8 0.84 v current source for direct ntc connection during normal operation during soft ? start v latch = 0 v i ntc i ntc(sstart) 65 130 95 190 105 210 a blanking duration on high latch detection 65 khz version 100 khz version t latch(ovp) 35 25 50 35 70 45 s blanking duration on low latch detection t latch(otp) ? 350 ? s clamping voltage i latch = 0 ma i latch = 1 ma v clamp0(latch) v clamp1(latch) 1.0 2.0 1.2 2.4 1.4 3.0 v temperature shutdown temperature shutdown t j going up t tsd 135 150 165 ? c temperature shutdown hysteresis t j going down t tsd(hys) 20 30 40 ? c
ncp1234 http://onsemi.com 8 typical performance characteristics 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 36.00 38.00 40.00 ? 50 ? 25 0 25 50 75 100 125 figure 3. minimum current source operation v hv(min) temperature ( ? c) v hv(min) (v) 0 5 10 15 20 25 30 35 ? 50 ? 25 0 25 50 75 100 12 5 figure 4. off ? state leakage current i start(off) temperature ( ? c) i start(off) (v) 0.65 0.66 0.67 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 ? 50 ? 25 0 25 50 75 100 125 v ilim (v) temperature ( ? c) figure 5. maximum internal current setpoint v ilim 0.95 0.97 0.99 1.01 1.03 1.05 1.07 1.09 1.11 1.13 1.15 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) v cs(stop) (v) figure 6. threshold for immediate fault protection activation v cs(stop) 40 50 60 70 80 90 100 110 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) t delay (ns) figure 7. propagation delay t dela y temperature ( ? c) t leb (ns) figure 8. leading edge blanking duration t leb 200 210 220 230 240 250 260 270 280 290 300 ? 50 ? 25 0 25 50 75 100 125
ncp1234 http://onsemi.com 9 typical performance characteristics 60 61 62 63 64 65 66 67 68 69 70 ? 50 ? 25 0 25 50 75 100 125 15 16 17 18 19 20 21 22 23 24 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) r fb(up) (k ) figure 9. fb pin internal pull ? up resistor r fb(up) 4.60 4.70 4.80 4.90 5.00 5.10 5.20 5.30 ? 50 ? 25 0 25 50 75 100 125 v fb(ref) (v) temperature ( ? c) figure 10. fb pin open voltage v fb(ref) temperature ( ? c) f osc (khz) figure 11. oscillator frequency f osc 75 76 77 78 79 80 81 82 83 84 85 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) d max (%) figure 12. maximum duty cycle d max 1.80 1.85 1.90 1.95 2.00 2.05 ? 50 ? 25 0 25 50 75 100 125 v fb(folds) (v) temperature ( ? c) figure 13. fb pin voltage below which frequency foldback starts v fb(folds) 1.20 1.25 1.30 1.35 1.40 1.45 1.50 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) v fb(folde) (v) figure 14. fb pin voltage below which frequency foldback is complete v fb(folde) 2.10 2.15 2.20
ncp1234 http://onsemi.com 10 typical performance characteristics 0.63 0.65 0.67 0.69 0.71 0.73 0.75 0.77 ? 50 ? 25 0 25 50 75 100 125 v skip(in) (v) temperature ( ? c) figure 15. fb pin skip ? in level v skip(in) 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86 0.88 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) v skip(out) (v) figure 16. fb pin skip ? out level v skip(out) 20 21 22 23 24 25 26 27 28 29 30 ? 50 ? 25 0 25 50 75 100 125 f osc(min) (khz) temperature ( ? c) figure 17. minimum switching frequency f osc(min) 110 115 120 125 130 135 140 145 150 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) i opc(365) ( a) figure 18. maximum overpower compensating current i opc(365) flowing out of cs pin 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 ? 50 ? 25 0 25 50 75 100 125 figure 19. fb pin level v fb(opcf) above which is the overpower compensation applied v fb(opcf) (v) temperature ( ? c) 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) v fb(opce) (v) figure 20. fb pin level v fb(opce) below which is no overpower compensation applied
ncp1234 http://onsemi.com 11 typical performance characteristics 2.35 2.40 2.45 2.50 2.55 2.60 2.65 ? 50 ? 25 0 25 50 75 100 125 v ovp (v) temperature ( ? c) figure 21. latch pin high threshold v ovp 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) v otp (v) figure 22. latch pin low threshold v otp 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 ? 50 ? 25 0 25 50 75 100 125 v clamp0 (v) temperature ( ? c) figure 23. latch pin open voltage v clamp0 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) v clamp1 (v) figure 24. latch pin voltage v clamp1 (latch ? off pin is sinking 1 ma) 70 75 80 85 90 95 100 105 110 ? 50 ? 25 0 25 50 75 100 125 temperature ( ? c) i ntc ( a) figure 25. current i ntc sourced from the latch pin, allowing direct ntc connection 140 150 160 170 180 190 200 210 220 ? 50 ? 25 0 25 50 75 100 125 i ntc(sstart) ( a) temperature ( ? c) figure 26. current i ntc(sstart) sourced from the latch pin, during soft ? start
ncp1234 http://onsemi.com 12 application information introduction the ncp1234 includes all necessary features to build a safe and efficient power supply based on a fixed ? frequency flyback converter. it is particularly well suited for applications where low part count is a key parameter, without sacrificing safety. ? current ? mode operation with slope compensation : the primary peak current is permanently controlled by the fb voltage, ensuring maximum safety: the drv turn ? off event is dictated by the peak current setpoint. it also ensures that the frequency response of the system stays a first order if in dcm, which eases the design of the fb loop. the controller can be also used in ccm applications with a wide input voltage range thanks to its fixed ramp compensation that prevents the appearance of sub ? harmonic oscillations in most applications. ? fixed ? frequency oscillator with jittering : the ncp1234 is available in different frequency options to fit any application. the internal oscillator features a low ? frequency jittering that helps passing the emi limits by spreading out the energy content of frequency peaks in quasi ? peak and average mode of measurement. ? latched timer ? based overload protection : the overload protection depends only on the fb signal, making it able to work with any transformer, even with very poor coupling or high leakage inductance. the protection is fully latched on the a version (the power supply has to be stopped then restarted in order to resume operation, even if the overload condition disapears), and autorecovery on the b version. the timer duration is fixed. the controller also enters the same protection mode if the voltage on the cs pin reaches 1.5 times the maximum internal setpoint (allows to detect winding short-circuits). ? high voltage start ? up current source : thanks to on semiconductor?s very high voltage technology, the ncp1234 can directly be connected to the high input voltage. the start-up current source ensures a clean start-up while ensuring low losses when it is off, and the dynamic self-supply (dss) restarts the start-up current source to supply the controller if the v cc supply transiently drops. ? adjustable overpower compensation : the high input voltage sensed on the hv pin is converted into a current to build on the current sense voltage an offset proportional to the input voltage. by choosing the value of the resistor in series with the cs pin, the amount of compensation can be adjusted to the application. ? frequency foldback then skip mode for light load operation : in order to ensure a high efficiency under all load conditions, the ncp1234 implements a frequency foldback for light load condition and a skip mode for extremely low load condition. the switching frequency is decreased down to 27 khz to reduce switching losses. ? extended vcc range : the ncp1234 accepts a supply voltage as high as 28 v, with an overvoltage threshold v cc(ovp) (typically 26.5 v) that latches the controller off. ? clamped driver stage : despite the high maximum supply voltage, the voltage on drv pin is safely clamped below 16 v, allowing the use of any standard mosfet, and reducing the current consumption of the controller. ? dual latch ? off input : the ncp1234 can be latched off by 2 ways: the voltage increase applied to its latch pin (typically an overvoltage) or by a decrease this voltage. thanks to the internal precise pull ? up current source a ntc can be directly connected to the latch pin. this ntc will provide an overtemperature protection by decreasing its resistance and consequently the voltage at latch pin, ? soft ? start : at every start ? up the peak current is gradually increased during 4.0 ms to minimize the stress on power components. ? temperature shutdown : the ncp1234 is internally protected against self ? overheating: if the die temperature is too high, the controller shuts all circuitries down (including the hv start ? up current source), allowing the silicon to cool down before attempting to restart. this ensures a safe behavior in case of failure. typical operation ? start ? up : the hv start ? up current source ensures the charging of the v cc capacitor up to the start ? up threshold v cc(on) , until the input voltage is high enough (above v hv(start) ) to allow the switching to start. the controller then delivers pulses, starting with a soft ? start period t sstart during which the peak current linearly increases before the current ? mode control takes over. during the soft ? start period, the low level latch is ignored, and the latch current is double, to ensure a fast pre ? charge of the latch pin decoupling capacitor. ? normal operation : as long as the feedback voltage is within the regulation range and v cc is maintained above v cc(min) , the ncp1234 runs at a fixed frequency (with jittering) in current ? mode control. the peak current (sensed on the cs pin) is set by the voltage on the fb pin. fixed ramp compensation is applied internally to prevent sub ? harmonic oscillations from occurring. ? light load operation : when the fb voltage decreases below v fb(folds) , typically corresponding to a load of
ncp1234 http://onsemi.com 13 33% of the maximum load (for a dcm design), the switching frequency starts to decrease down to f osc(min) . by lowering the switching losses, this feature helps to improve the efficiency in light load conditions. the frequency jittering is enabled in light load operation as well. ? no load operation : when the fb voltage decreases below v skip(in) , typically corresponding to a load of 2% of the maximum load, the controller enters skip mode. by completely stopping the switching while the feedback voltage is below v skip(out) , the losses are further reduced. this allows minimizing the power dissipation under extremely low load conditions. as the skip mode is entered at very light loads, for which the peak current is very small, there is no risk of audible noise. v cc can be maintained between v cc(on) and v cc(min) by the dss, if the auxiliary winding does not provide sufficient level of v cc voltage under this condition. ? overload : the ncp1234 features timer ? based overload detection, solely dependent on the feedback information: as soon as the internal peak current setpoint hits the v ilim clamp, an internal timer starts to count. when the timer elapses, the controller stops and enter the protection mode, autorecovery for the b version (the controller initiates a new start ? up after t autorec elapses), or latched for the a version (the latch is released only if v cc is reset). ? latch ? off : when the latch input is pulled up (typically by an over ? voltage condition), or pulled down (typically by an over ? temperature condition, using the provided current source with an ntc), the controller latches off. the latch is released when the v cc is reset.
ncp1234 http://onsemi.com 14 detailed description high ? voltage current source the ncp1234 hv pin can be connected either to the rectified bulk voltage, or to the ac line through a rectifier. however, the overpower compensation will work correctly only if the hv pin is connected to the bulk voltage. start ? up ? + ? + + + r s q tsd hv vcc i start v cc(on) v cc(off ) t uvlo(blank) blanking control uvlo ? + + v cc(reset) reset ic start ? + + v cc(min) figure 27. hv start ? up current source functional schematic at start ? up, the current source turns on when the voltage on the hv pin is higher than v hv(min) , and turns off when v cc reaches v cc(on) , then turns on again when v cc reaches v cc(min) , until v cc is supplied by an internal source. the controller actually starts the next time v cc reaches v cc(on) . even though the dss is able to maintain the v cc voltage between v cc(on) and v cc(min) by turning the hv start ? up current source on and off, it can only be used in light load condition, otherwise the power dissipation on the die would be too much. as a result, an auxiliary voltage source is needed to supply v cc during normal operation. the dss is useful to keep the controller alive when no switching pulses are delivered, e.g. in latch condition, or to prevent the controller from stopping during load transients when the v cc might drop.
ncp1234 http://onsemi.com 15 figure 28. start ? up timing diagram time v hv time v cc time drv v hv(min) v cc(on) v cc(min) v cc(inhibit) hv current source = i start1 hv current source = i start2 for safety reasons, the start ? up current is lowered when v cc is below v cc(inhibit) , to reduce the power dissipation in case the v cc pin is shorted to gnd (in case of v cc capacitor failure, or external pull ? down on v cc to disable the controller). there are only two conditions for which the current source doesn?t turn on when v cc reaches v cc(min) : the voltage on hv pin is too low (below v hv(min) ), or a thermal shutdown condition (tsd) has been detected. in all other conditions, the hv current source will always turn on and of f to maintain v cc between v cc(min) and v cc(on) . when the application is turned off, the input capacitor quickly discharges, and the output starts to fall out of regulation. at the same time, v cc drops, but because there is no voltage anymore on the hv pin, the dss isn?t able to turn on. as a result, v cc drops even more and reach the v cc(off) threshold, that turns the controller off, and resets the internal fault timer, to prevent any unwanted latch ? off and allow a fast restart in case of a short off/on sequence. as soon as the application is turned back on, the hv start ? up current source starts to charge the v cc capacitor. note that the threshold at which v cc discharges has no influence on the ability of the controller to restart. the switching then turns on when v cc reaches v cc(on) , without additional delay or ?hiccup?.the case of a fast off/on sequence is described at figure 29.
ncp1234 http://onsemi.com 16 figure 29. fast application off ? on sequence time v hv time v cc time output v hv(min) v cc(on) v cc(min) the board is unplugged controller stops at v cc(off) v cc(off) time drv time fault timer (internal) vcc charges up when v hv is high enough loss of regulation when v hv is too low switching restarts at v cc(on) fault timer reset by v cc(off)
ncp1234 http://onsemi.com 17 oscillator with maximum duty cycle and frequency jittering the ncp1234 includes an oscillator that sets the switching frequency with an accuracy of ? 7%. two frequency options can be ordered: 65 khz and 100 khz. the maximum duty cycle of the drv pin is 80%, with an accuracy of ? 7%. in order to improve the emi signature, the switching frequency jitters ? 6% around its nominal value, with a triangle ? wave shape and at a frequency of 125 hz. this frequency jittering is active even when the frequency is decreased to improve the emi in light load condition. time 8% (125 hz) figure 30. frequency jittering f osc f osc + 6 nominal f osc f osc ? 6 clamped driver the supply voltage for the ncp1234 can be as high as 28 v, but most of the mosfets that will be connected to the drv pin cannot accept more than 20 v on their gate. the driver pin is therefore clamped safely below 16 v. this driver has a typical current capability of ? 500 ma. figure 31. clamped driver drv clamp drv signal vcc
ncp1234 http://onsemi.com 18 current ? mode control with overpower compensation and soft ? start current sensing ncp1234 is a current ? mode controller, which means that the fb voltage sets the peak current flowing in the inductance and the mosfet. this is done through a pwm comparator: the current is sensed across a resistor and the resulting voltage is applied to the cs pin. it is applied to one input of the pwm comparator through a 250 ns leb block. on the other input the fb voltage divided by 5 sets the threshold: when the voltage ramp reaches this threshold, the output driver is turned off. the maximum value for the current sense is 0.7 v, and it is set by a dedicated comparator. figure 32. current sense block schematic cs fb ? + t leb blanking k fb r fb(up) ? + ? + ? + + + v ilim v cs(stop) s r q t sstart soft ? start ramp start reset ic start ic stop oscillator protection mode uvlo jitter latch soft ? start ic stop tsd fault drv stage blanking pwm t bcs v fb(ref) each time the controller is starting, i.e. the controller was off and starts ? or restarts ? when v cc reaches v cc(on) , a soft ? start is applied: the current sense setpoint is linearly increased from 0 (the minimum level can be higher than 0 because of the leb and propagation delay) until it reaches v ilim (after a duration of t sstart ), or until the fb loop imposes a setpoint lower than the one imposed by the soft ? start (the 2 comparators outputs are or?ed). the soft ? start ramp signal is generated by the d/a converter in the ncp1234, that?s why there are observable 15 discrete steps instead the truly linearly increasing current setpoint ramp.
ncp1234 http://onsemi.com 19 time v fb v fb(fault) time soft-start ramp v ilim t sstart time cs setpoint v ilimi v fb takes over soft-start figure 33. soft ? start under some conditions, like a winding short ? circuit for instance, not all the energy stored during the on time is transferred to the output during the off time, even if the on time duration is at its minimum (imposed by the propagation delay of the detector added to the leb duration). as a result, the current sense voltage keeps on increasing above v ilim , because the controller is blind during the leb blanking time. dangerously high current can grow in the system if nothing is done to stop the controller. that?s what the additional comparator, that senses when the current sense voltage on cs pin reaches v cs(stop) (= 1.5 x v ilim ), does: as soon as this comparator toggles, the controller immediately enters the protection mode (latched or autorecovery according to the chosen option). overpower compensation the power delivered by a flyback power supply is proportional to the square of the peak current in the discontinuous conduction mode: p out 1 2 l p f sw i p 2 (eq. 1) unfortunately, due to the inherent propagation delay of the logic, the actual peak current is higher at high input voltage than at low input voltage, leading to a significant difference in the maximum output power delivered by the power supply.
ncp1234 http://onsemi.com 20 time i p high line low line i limit t delay t delay i p to be compensated figure 34. line compensation for true overpower protection to compensate this and have an accurate overpower protection, an offset proportional to the input voltage is added on the cs signal by turning on an internal current source: by adding an external resistor in series between the sense resistor and the cs pin, a voltage offset is created across it by the current. the compensation can be adjusted by changing the value of the resistor. but this offset is unwanted to appear when the current sense signal is small, i.e. in light load conditions, where it would be in the same order of magnitude. therefore the compensation current is only added when the fb voltage is higher than v fb(opce) . however, because the hv pin can be connected to an ac voltage, there is needed an additional circuitry to read or at least closely estimate the actual voltage on the bulk capacitor. figure 35. schematic overpower compensation circuit a/d 3 bit converter + peak detector t blanking leb watch dog hv cs fb v hvstop (32 ms) 3 bit register i generator v fb (opc) to c s block i ctrl a 3 bit a/d converter with the peak detector senses the ac input, and its output is periodically sampled and reset, in order to follow closely the input voltage variations. the sample and reset events are given by the v hvsample comparator used for sampling detection for the ac line input. if only the dc high voltage input is used, no reset signal is generated by the v hvsample condition and the 32 ms watch dog is used to generate the sampling events for sampling the dc input high voltage line.
ncp1234 http://onsemi.com 21 v fb i opc v fb(opce) v fb(opcf) v hv figure 36. overpower compensation current relation to feedback voltage and input voltage figure 37. overpower compensation current if the hv pin is connected to ac voltage time v hv time peak detector v hvsample t wd time i opc sample sample sample sample reset reset reset reset reset reset
ncp1234 http://onsemi.com 22 time time peak detector time sample sample sample reset reset v hv v hv(stop) i opc figure 38. overpower compensation if the hv pin is connected to dc voltage t wd t wd t wd t hv feedback with slope compensation the ratio from the fb voltage to the current sense setpoint is 5, meaning that the fb voltage corresponding to v ilim is 3.5 v. there is a pull ? up resistor of 20 k from fb pin to an internal reference. cs fb ? + blanking 20 k k fb pwm v fb(ref) figure 39. fb circuitry t leb in order to allow the ncp1234 to operate in ccm with a duty cycle above 50%, a fixed slope compensation is internally applied to the current ? mode control. the slope appearing on the internal voltage setpoint for the pwm comparator is ? 32.5 mv/ s typical for the 65 khz version, and ? 50 mv/ s for the 100 khz version.
ncp1234 http://onsemi.com 23 overcurrent protection with fault timer when an overcurrent occurs on the output of the power supply, the fb loop asks for more power than the controller can deliver, and the cs setpoint reaches v ilimit . when this event occurs, an internal t fault timer is started: once the timer times out, drv pulses are stopped and the controller is either latched off (latched protection, version a), or it enters an autorecovery mode (version b). the timer is reset when the cs setpoint goes back below v ilim before the timer elapses. to provide maximum output power at the low input line voltages the fault timer is not started if the driver signal is reset by the max duty cycle. cs fb ? + t leb blanking / 5 ? + + v ilim protection mode t fault timer release t autorec timer reset autorecovery protection mode only r s q pwm reset drv figure 40. timer ? based overcurrent protection
ncp1234 http://onsemi.com 24 in autorecovery mode, the controller tries to restart after t autorec . if the fault has gone, the supply resumes operation; if not, the system starts a new burst cycle. time fault flag time v cc time drv v cc(on) v cc(min) overcurrent applied time output load max load time fault timer t fault fault timer starts controller stops fault disappears t fault t autorec restart at v cc(on) (new burst cycle if fault still present) figure 41. autorecovery timer ? based protection mode
ncp1234 http://onsemi.com 25 in the latched version, the controller can restart only if a v cc reset occurs, which in a real application can only happen if the power supply is unplugged from the mains line. time fault flag time v cc time drv v cc(on) v cc(min) overcurrent applied time output load max load time fault timer t fault fault timer starts controller latches off no restart when fault disappears t fault figure 42. latched timer ? based overcurrent protection
ncp1234 http://onsemi.com 26 low load operation frequency foldback in order to improve the efficiency in light load conditions, the frequency of the internal oscillator is linearly reduced from its nominal value down to f osc(min) . this frequency foldback starts when the voltage on fb pin goes below v fb(folds) , and is complete before v fb reaches v skip(in) , whatever the nominal switching frequency option is. the current ? mode control is still active while the oscillator frequency decreases. note that the frequency foldback is disabled if the controller runs at its maximum duty cycle. fb f osc nominal f osc v skip(in) v fb(folds) f osc(min) skip figure 43. frequency foldback when the fb voltage decreases v fb(folde) skip cycle mode figure 44. skip cycle schematic ? + cs s r q fb blanking ? + + drv stage v skip k fb t leb when the fb voltage reaches v skip(in) while decreasing, skip mode is activated: the driver stops, and the internal consumption of the controller is decreased. while v fb is below v skip(out) , the controller remains in this state; but as soon as v fb crosses the skip out threshold, the drv pin starts to pulse again.
ncp1234 http://onsemi.com 27 time time drv enters skip exits skip enters skip exits skip figure 45. skip cycle timing diagram v fb v fb(fold) v skip(out) v skip(in) latch ? off input figure 46. latch detection schematic ? + latch v ovp s r q ? + v otp t latch(ovp) blanking vdd reset latch v clamp i ntc t latch(otp) blanking 1 k i ntc + + soft ? start end the latch pin is dedicated to the latch ? off function: it includes two levels of detection that define a working window, between a high latch and a low latch: within these two thresholds, the controller is allowed to run; but as soon as either the low or the high threshold is crossed, the controller is latched off. the lower threshold is intended to be used with an ntc thermistor, thanks to an internal current source i ntc . an active clamp prevents the voltage from reaching the high threshold if it is only pulled up by the i ntc current. to reach the high threshold, the pull ? up current has to be higher than the pull ? down capability of the clamp (typically 1.5 ma at v ovp ). to avoid any false triggering, spikes shorter than 50 s (for the high latch and 65 khz version) or 350 s (for the low latch) are blanked and only longer signals can actually latch the controller. reset occurs when v cc is cycled down to a reset voltage, which in a real application can only happen if the power supply is unplugged from the ac line. upon start ? up, the internal references take some time before being at their nominal values; so one of the comparators could toggle even if it should not. therefore the internal logic does not take the latch signal into account before the controller is ready to start: once v cc reaches v cc(on) , the latch pin high latch state is taken into account
ncp1234 http://onsemi.com 28 and the drv switching starts only if it is allowed; whereas the low latch (typically sensing an overtemperature) is taken into account only after the soft ? start is finished. in addition, the ntc current is doubled to i ntc(sstart) during the soft ? start period, to speed up the charging of the latch pin capacitor. the maximum value of latch pin capacitor is given by the following formula (the standard start ? up condition is considered and the ntc current is neglected) : c latchmax t sstartmin i ntc(sstart)min v clamp0min (eq. 2) 2.8 10 ? 3 130 10 ? 6 1.0 f 364 nf time internal latch signal time v cc time drv v cc(on) v cc(min) latch signal high during pre-start phase noise spike ignored (t latch blanking) start-up initiated by v cc(on) switching allowed (no latch event) latch-off figure 47. latch ? off function timing diagram temperature shutdown the die includes a temperature shutdown protection with a trip point guaranteed above 135 ? c and below 165 ? c, and a typical hysteresis of 30 ? c. when the temperature rises above the high threshold, the controller stops switching instantaneously, and the hv current source is turned off. internal logic state is reset. when the temperature falls below the low threshold, the hv start ? up current source is enabled, and a regular start ? up sequence takes place.
ncp1234 http://onsemi.com 29 state diagrams hv start ? up current source stop i start1 i start2 off no tsd tsd tsd v cc > v cc(inhibit) v cc < v cc(inhibit) v cc > v cc(on) v cc < v cc(min) tsd tsd figure 48. hv start ? up current source state diagram
ncp1234 http://onsemi.com 30 controller operation (latched version: a option) figure 49. controller operation state diagram (latched protection) stopped running ? fault ? tsd v cc >v cc(on) ? tsd skip out with fault= ? t fault expires ? v cs >v cs(stop) soft ? start soft ? start ends skip skip in ? tsd ? tsd latch ? vcc reset ? high latch ? v cc v cc(ovp) ? v cc >v cc(ovp) ? v cc >v cc(ovp)
ncp1234 http://onsemi.com 31 controller operation (autorecovery version: b option) stopped running ? fault ? tsd v cc >v cc(on) ? t autorec counting ? tsd skip out with fault= ? t fault expires ? v cs >v cs(stop) ? v cc v cc(ovp) ? high latch ? low latch ? v cc >v cc(ovp) ? high latch ? low latch ? v cc >v cc(ovp) figure 50. controller operation state diagram (autorecovery protection) ? v cc ncp1234 http://onsemi.com 32 table 1. ordering information part no. overload protection switching frequency package shipping ? NCP1234AD65R2G latched 65 khz soic ? 7 (pb ? free) 2500 / tape & reel ncp1234bd65r2g autorecovery 65 khz soic ? 7 (pb ? free) 2500 / tape & reel ncp1234ad100r2g latched 100 khz soic ? 7 (pb ? free) 2500 / tape & reel ncp1234bd100r2g autorecovery 100 khz soic ? 7 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1234 http://onsemi.com 33 package dimensions soic ? 7 case 751u ? 01 issue e seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? a ? ? b ? g m b m 0.25 (0.010) ? t ? b m 0.25 (0.010) t s a s m 7 pl 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1234/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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